1. Field of the Invention
The present invention generally relates to TLB (Translation Lookaside Buffer for translation from logical addresses to physical addresses) incorporated in a processor such as a central processing device, and more particularly, to reduction in electric power consumption for TLB.
2. Description of the Related Art
Recent development of high-speed processors (central processing devices) has promoted higher operation speed of transistor elements in the processors. The faster operation of a transistor element is achieved by lowering a threshold voltage (Vth) of the transistor element and thereby raising the current level (Ids) of the activated transistor element. When such transistors are used to design a processor, it is possible to drastically improve operation frequency of the processor.
However, if a transistor element has a lower threshold voltage (Vth) as noted above, the off-state leakage current may increase when the transistor element is off-state. That results in increases in electric power consumption during inactivation of the processor.
In particular, as disclosed in “Design challenges of technology scaling”, IEEE Micro, 19, 4, 1999 presented by S. Borkar, a larger amount of static electric power would be consumed in a cache RAM within the processor during inactivation of the processor. Since an existing processor includes a large number of cache RAMs and a large area within the processor is occupied by the cache RAMs, it is estimated that the processor consumes an amount of power corresponding to about 5-10% of electric power for normal operation as static electric power, the amount of which tends to increase in future.
Also, some proposals to overcome the above problem have been presented. The article, which was written by C. H. Kim, “Dynamic Vt SRAM: A Leakage Tolerant Cache Memory for Low Voltage Microprocessors”, ISLPED02, Aug. 12-14, 2002 discloses a method of lowering a leakage current by dynamically changing the threshold voltage (Vt) of a transisitor. “Cache Decay: Exploiting Generational Behavior to Reduce Cache Leakage Power”, ISCA, 2001 discloses an approach to reduce power consumption by invalidating cache lines below a predefined frequency of use.
Moreover, some conventional techniques relating to the present invention are described in Japanese Laid-Open Patent Applications No. 07-334423, No. 56-035228B and No. 09-204359.
However, although TLB within a processor consumes electric power like cache RAMs, little attention on reduction in power consumption has been focused on TLB because of dominant seeking of speedup of TLB.
In TLB, CAM (Content Addressable Memory) includes high-speed circuits such as dynamic circuits. As a result, TLB consumes a large amount of electric power during normal operation as well as inactivation. Especially, TLB needs to include an additional extra charging circuit to eliminate some problems such as charge-sharing occurring in such a dynamic circuit in a comparator circuit within CAM. Thus, it is impossible to easily reduce electric power consumption during normal operation and inactivation.
In order to improve address translation performance of TLB, a larger number of entries are often provided within TLB. That increases an unnecessary amount of leakage current, resulting in further increases in power consumption.